Sar Adc Phd Thesis

Sar Adc Phd Thesis-51
A time-interleaved structure is employed to improve the effective sampling rate without sacrificing energy efficiency.

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Traditionally, ADCs are considered a power hungry circuit.

They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. Analog-to-digital converters (ADCs) are essential building blocks in many electronic systems which require digital signal processing and storage of analog signals.

The zero-crossing based circuit technique is modified and optimized to improve the limited ADC resolution in nano-scaled CMOS technology.

This thesis investigates ADC design techniques to achieve high-performance with low power consumption. The first design is a voltage scalable zero-crossing based pipelined ADC.

Because the full-speed flash ADC does not suffer from timing-skew errors, the flash ADC output is also used as the timing reference to estimate the timing-skew of the SAR ADCs.

The main contributions include investigation of using digital error correction (redundancy) in SAR ADCs for dynamic error correction and speed improvement, development of two new calibration algorithms to digitally correct for manufacturing mismatches, design of new architecture to incorporate redundancy within the architecture itself while achieving 94% better energy eciency compared to conventional switching algorithm, development of a new capacitor DAC structure to improve the SNR by four times with improved matching, joint design of the analog and digital circuits to create an asynchronous platform in order to reach the targeted performance, and analysis of key circuit blocks to enable the design to meet noise, power and timing requirements.

They may be viewed from this source for any purpose, but reproduction or distribution in any format is prohibited without written permission. As technology scales, the improved speed and energy eciency make the successive- approximation-register (SAR) architecture an attractive alternative for applications that require high-speed and high-accuracy analog-to-digital converters (ADCs).

The design is fabricated in standard 1P9M 65nm CMOS technology with 1.2V supply.

It is far from straightforward to achieve such low power consumptions and still be able to digitize the analog signals with sufficient speed and precision.

Pieter Harpe has contributed to more than 100 scientific publications and 7 patents.

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